1. Field of the Invention
The present invention relates to a Dynamic Random Access Memory (DRAM) and a semiconductor device including same.
2. Description of the Related Art
FIG. 8 is a circuit diagram showing part of a prior art DRAM.
In a memory cell 10, one end of a capacitor 11 is connected through a transfer gate 12 to a bit line *BL, and in a memory cell 20, one end of a capacitor 21 is connected through a transfer gate 22 to a bit line BL. A potential Vpr=Vii/2 is applied to the other ends of the capacitors 11 and 21, where Vii is an internal power-supply voltage, e.g., 3.0 V. The gates of the transfer gates 12 and 22 are respectively connected to word lines WL0 and WL1.
When the contents of a memory cell, the cell 10 for instance, are to be read out, the bit lines BL and *BL are set to a precharge potential Vpr, then the transfer gate 12 is set to on for a proper time and the difference between the potentials of the bit line BL and the bit line *BL is amplified by a sense amplifier 30. When writing data in the memory cell 10, the bit line *BL is set to 0 V (writing a lower level "L") or to the internal power-supply potential Vii (writing a higher level "H") with the transfer gate 12 being on after said amplification, next the transfer gate 12 is turned off.
The solid lines in FIG. 9(A) indicate the waveforms of the voltages at the word line WL0 and the bit line *BL in reading out "L" from the memory cell 10, and the solid lines in FIG. 9(B) indicate waveforms of the voltages at the word line WL0 and the bit line *BL in reading out "H" from the memory cell 10.
Due to miniaturization of circuit elements and lowering operating voltages, the potential change .DELTA. of the bit line *BL in readout becomes reduced. In addition, the ratio of the current leak at the capacitor 11 to the electrical charge held by the capacitor 11 increases. The current leak occurring when "H" is held in the capacitor 11 is larger than that occurring when "L" is held in the capacitor 11. Since, if the potential change .DELTA. is too small, the sense amplifier operates erroneously, resulting in erroneous data readout, so it is necessary to give the potential change .DELTA. a sufficient margin which allows the potential difference between the bit line BL and the bit line *BL to be amplified without the sense amplifier 30 operating erroneously.
Thus, in the prior art, the source and the drain of an nMOS transistor 31 are connected to the bit line *BL with its gate connected to a dummy word line DWLO, and likewise, an nMOS transistor 32 is connected between the bit line BL and a dummy word line DWL1. When reading out the contents of the memory cell 10, the potential of the word line WL0 is shifted to high to turn on the transfer gate 12, and at the same time, the potential of the dummy word line DWL0 is shifted from 0 V to the internal power-supply potential Vii to supplement a positive charge to the bit line *BL in order to compensate for the reduction in the potential change .DELTA. due to the current leak at the capacitor 11. The alternate long and short lines in FIGS. 9(A) and 9(B) indicate waveforms of the voltages at the bit line *BL when such a compensating operation is performed.
However, since a positive charge, which is equal to or exceeding that supplemented to the bit line *BL in "H" readout, is supplemented to the bit line *BL in "L" readout, the margin contained in the potential change .DELTA. in "L" readout is reduced, presenting a disadvantage.